(Peer-Reviewed) A compression-decompression framework for universal acceleration of photonic neuromorphic computing
Changdi Zhou ¹ ², Deyu Cai ¹ ², Yu Huang ¹ ², Yigong Yang ¹ ², Pei Zhou ¹ ², Kuenyao Lau ¹ ², Nianqiang Li ¹ ²
¹ School of Optoelectronic Science and Engineering & Collaborative Innovation Center of Suzhou Nano Science and Technology, Soochow University, Suzhou 215006, China
中国 苏州 苏州大学光电科学与工程学院 苏州纳米科技协同创新中心
² Key Laboratory of Advanced Optical Manufacturing Technologies of Jiangsu Province & Key Laboratory of Modern Optical Technologies of the Ministry of Education, Soochow University, Suzhou 215006, China
中国 苏州 苏州大学江苏省先进光学制造技术重点实验室 教育部现代光学技术重点实验室
Opto-Electronic Advances, 2026-03-06
Abstract
Photonic neuromorphic computing provides an effective route to overcoming the fundamental bottlenecks of the von Neumann architecture. However, the realization of complex optical nonlinearities by time-division multiplexing in traditional photonic neuromorphic computing limits both information-processing speed and scalability of these systems.
Here, we break this bottleneck by introducing an accuracy-compensated compression strategy that co-optimizes latency and speed without sacrificing computational fidelity. Our core innovation is an eigenvector-driven compression-decompression framework that projects input data into a task-relevant subspace, drastically reducing the data volume processed by the hidden layer. This paradigm shift enables photonic neuromorphic computing to achieve image recognition and time-series prediction tasks in the optical domain at speeds of 100 million images and 600 million data points per second, respectively.
We experimentally validate our approach across both a continuous-wave system based on off-the-shelf lasers and a spiking system composed of a specifically fabricated photonic neuro-synaptic chip, demonstrating that the compression-decompression framework effectively recovers the accuracy to the level of uncompressed networks—e.g., achieving >95% on MNIST and >84% on Fashion-MNIST—while slashing latency and hardware resource demands by an order of magnitude.
This strategy establishes a scalable pathway towards high-throughput, low-power neuromorphic chips, bridging a critical gap between algorithmic efficiency and physical computing paradigms.
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